Search found 3 matches
- Tue Jan 31, 2017 6:07 pm
- Forum: FAQ about Tulipp Development Platform
- Topic: FMC Banks and Voltage
- Replies: 6
- Views: 5918
Re: FMC Banks and Voltage
Hi Tim, Could you clarify why using LVDS_25, setting JP8 to 2.5V, and configuring the inputs in Vivado with DIFF_TERM TRUE would damage the FPGA? I really believe there is a way around, if all the signals in the FMC are inputs of the system. The HP bank VCCO can only go upto 1.89V as per this docume...
- Wed Jan 18, 2017 12:35 am
- Forum: FAQ about Tulipp Development Platform
- Topic: FMC Banks and Voltage
- Replies: 6
- Views: 5918
Re: FMC Banks and Voltage
Please Note:
When using Z7030 JP8 (jumper to determine the VCCIO for bank 13 and 35) must be on position 2-3 for 1.8V. Any other setting will damage the FPGA.
When using Z7030 JP8 (jumper to determine the VCCIO for bank 13 and 35) must be on position 2-3 for 1.8V. Any other setting will damage the FPGA.
- Wed Jan 18, 2017 12:28 am
- Forum: FAQ about Tulipp Development Platform
- Topic: FMC Banks and Voltage
- Replies: 6
- Views: 5918
Re: FMC Banks and Voltage
Hi Carl, You are right the EMC2 Z7030 board uses both banks so in order to get the FMC_CL working you have to use LVDS_25 for pins on bank 13 and LVDS for pins on bank 35 without internal termination. I just looked at the Alpha data board pinout http://www.alpha-data.com/pdfs/fmc-cameralink%20user%2...