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Well, my guess seeing that a standalone application works like a charm, whereas programming with a debugger that is not the Xilinx one, is that something is messing the JTAG chain up. Why do I say this? Because the CPLD is related to the JTAG chain, and I don't think it's a coincidence that it work...

Do you have a Xilinx pod around to configure the FPGA through JTAG? In this way we could discard HIPPEROS/other pods as the possible problem. Just to be sure it's a hardware issue. We tried to program with the JTAG HS3 using a very simple design from Vivado. It also was not working. We do not have ...

Is this TE0820-3EG-02 or TE0715-30-03? I think it's TE0715-30-03. It is TE0715-30-03. I looked into the same documentation of the trenz module you mentioned: https://wiki.trenz-electronic.de/display/PD/TE0715+TRM . The red LED (D3) is blinking. From my understanding that means the Done Signal is 0 ...