FMC Banks and Voltage

[Carl_Ehrenstrahle]

This is less of a question and more like general information/insight.

For the Z7030 chips the FMC signals are routed to two different banks, bank 13 and 35. Bank 13 is a HR bank and bank 35 is a HP bank.
This difference has an impact when it comes to differential signaling, especially LVDS with internal termination.
HR banks support the LVDS_25 IO standard. LVDS_25 requires a VCCIO of 2.5V for output and the use of the internal termination option.
HP banks support the LVDS IO standard. LVDS requires a VCCIO of 1.8V for output and the use of the internal termination option.
See this link for more information about LVDS and VCCIO: https://www.xilinx.com/support/answers/43989.html .
This file contains the pin info for the Z7030 chip used on the TR0715: https://www.xilinx.com/support/packagef ... 485pkg.txt .

The EMC2 carrier board has a jumper to determine the VCCIO for bank 13 and 35 (JP8). Note that it drives both banks with the same voltage. This results in the inability to use the internal termination options on the bank which is not running its "native" voltage. It also affects your ability to use one of the banks as an output. Keep this in mind when using LVDS over the FMC.

[Stephen_Malchi]

Hi Carl,

You are right the EMC2 Z7030 board uses both banks so in order to get the FMC_CL working you have to use LVDS_25 for pins on bank 13 and LVDS for pins on bank 35 without internal termination.

I just looked at the Alpha data board pinout http://www.alpha-data.com/pdfs/fmc-came ... manual.pdf and EMC2_Z7030 pinout here http://www.sundance.technology/wp-conte ... -15-30.pdf.

This will have the same problem if LVDS IOSTANDARD is used. I guess in order to get this working they used "DIFF_SSTL18_II" IOSTANDARD for differential signals, which does not have internal termination and uses 1.8v VCCIO for output as well.

Please see table 1.55 of https://www.xilinx.com/support/document ... lectIO.pdf

I hope this helps.

Rgds,
Stephen

[Stephen_Malchi]

Please Note:

When using Z7030 JP8 (jumper to determine the VCCIO for bank 13 and 35) must be on position 2-3 for 1.8V. Any other setting will damage the FPGA.

[Timoteo]

Hi,

I want to add this information to what you know already, and hopefully you will make the Camera Link application work.

The TE0715-30 banks:
-Bank 12. It’s High Range.
-Bank 35. It’s High Performance.

The EMC2 carrier board has JP7 and JP8 to setup the voltages. JP7 is VCCIO 34 (bank we don’t care about here). JP8 is VCCIO 35.
VCCIO35 supplies the FMC VADJ, Bank 12, and Bank 35.

So, basically the FMC receives the corresponding 3.3V, 12V, plus VADJ which is 2.5V, the same as banks 12 and 35.
Bank 35 is HP, so it requires this:
-Signals used as outputs, are OK.
-Signals used as inputs, you need to enable DIFF_TERM.

We said in Sweden, that next step would be trying with 7015 module, and the zedboard.
The Ultrascale module has all its banks HP.
----------------------------

Thanks Stephen for your info, as I didnt check the application details, I dont know if 1.8 was required.
Added this info hopefully it will be working soon!

Regards
Timoteo

[Timoteo]

Please Note:

When using Z7030 JP8 (jumper to determine the VCCIO for bank 13 and 35) must be on position 2-3 for 1.8V. Any other setting will damage the FPGA.

Could you clarify why using LVDS_25, setting JP8 to 2.5V, and configuring the inputs in Vivado with DIFF_TERM TRUE would damage the FPGA?
I really believe there is a way around, if all the signals in the FMC are inputs of the system.

The camera recommends 1.8V, but accepts 1.8 up to 3.3V.
Regards,
Timoteo

[Stephen_Malchi]

Hi Tim,

Could you clarify why using LVDS_25, setting JP8 to 2.5V, and configuring the inputs in Vivado with DIFF_TERM TRUE would damage the FPGA?
I really believe there is a way around, if all the signals in the FMC are inputs of the system.

The HP bank VCCO can only go upto 1.89V as per this document please see table 13 page 10

https://www.xilinx.com/support/document ... _Sheet.pdf

From what I understand, Vivado will throw an error if HP pins are used as LVDS_25 with termination. Same when HR pins are used as LVDS with termination because these banks do not support both IO_Standards. Please see Table 1-55 and look for LVDS, LVDS_25 standards on page 99.

https://www.xilinx.com/support/document ... lectIO.pdf

Also please see note 1 and 2

I dont know what Xilinx's recommendation is for connecting 2.5v VCCO to HP bank. If they say its ok then we can do it, but still cant use the same IO_standard on both banks with termination.

The best we can do is use 1.8v for both banks as it is supported and use LVDS standard with no input termination for both banks.

Rgds,
Stephen

[Timoteo]

Hi Tim,

Could you clarify why using LVDS_25, setting JP8 to 2.5V, and configuring the inputs in Vivado with DIFF_TERM TRUE would damage the FPGA?
I really believe there is a way around, if all the signals in the FMC are inputs of the system.

The HP bank VCCO can only go upto 1.89V as per this document please see table 13 page 10

https://www.xilinx.com/support/document ... _Sheet.pdf

From what I understand, Vivado will throw an error if HP pins are used as LVDS_25 with termination. Same when HR pins are used as LVDS with termination because these banks do not support both IO_Standards. Please see Table 1-55 and look for LVDS, LVDS_25 standards on page 99.

https://www.xilinx.com/support/document ... lectIO.pdf

Also please see note 1 and 2

I dont know what Xilinx's recommendation is for connecting 2.5v VCCO to HP bank. If they say its ok then we can do it, but still cant use the same IO_standard on both banks with termination.

The best we can do is use 1.8v for both banks as it is supported and use LVDS standard with no input termination for both banks.

Rgds,
Stephen

Right, so what's the inconvenient on using LVDS on bank 13?
Setting the board with 1.8V, using LVDS on the HP bank with DIFF_TERM TRUE, and LVDS on bank 13 should do it.

I honestly thought there were inputs and outputs in this picture, but it seems the FPGA receives all the FMC signals as inputs. One way or another it's possible to do it I think.

Thanks for your answer, I had a confusion with the voltage
Timoteo