Support.Tulipp.eu

Hi,

Here I attach a .bit file to test the leds on the board, so that you can check fast if programming the FPGA through JTAG works fine.
Just open hardware manager, and select the .bit file to program the FPGA.



Regards,

Timoteo

Thanks Timoteo.

I am unable to connect to the device using Vivado Hardware Manager. Can you please help?

I get this error in Vivado:

ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
Targets(s) ", jsn-DLC10-000013e2173401" may be locked by another hw_server.

I am able to see an orange light on my Xilinx Platform Cable USB box.
Is this correct?

How should the jumpers 1-3 look like to program from JTAG?
Right now I have shorted jumpers 1 and 2.

Best regards,
Ananya

If it complains about hw_server, it means you have another Vivado open, or there is a process of the hardware manager still open. I suggest you check the task manager, and end all the processes related to Vivado, specially the one called hw_server, and try again.

The jumper at JP11, just leave it open, as its 1-2 for QSPI, and 2-3 for SD card. JP12 installed, that test uses the PCIe reference clock.

Regards,
Timoteo

Thanks for the test file Timoteo!

Dear Timoteo,

Could you provide the source files/vivado project behind the generation of this bit file?
The bit file works fine through JTAG but we are trying to use dynamic partial reconfiguration (DPR) within HIPPEROS on the EMC2 board but the bit file is made for JTAG (with headers, etc.), then we must generate another bitstream file to use DPR.

Thank you in advance,
Best regards,

Antonio

Hi,
It's a short VHDL code. It divides the PCIe reference clock and with that output clock toggles the LEDs.
Follow the link:
http://support.tulipp.eu/viewtopic.php?f=7&t=31

Regards,
Timoteo