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SDSoC 2017.4 issues with board parts

Posted: Tue Aug 21, 2018 11:34 am
by Giacomo_Valente
Dear all,
I am moving to SDSoC 2017.4 with Vivado and SDx, working with Ubuntu 16.04.2. It is the official supported version from Xilinx for these tools version. While testing the flow with the HDMI output application (with no input from camera, but simply taking an image) and testing the custom imported platform, correctly created with SDx, I obtain the following error (extracted from the sds.log file):

CRITICAL WARNING: [Board 49-71] The board_part definition was not found for sundance.com:emc²-z7030:part0:1.0. The project's board_part property was not set, but the project's part property was set to xc7z030sbg485-1. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command. Check if board.repoPaths parameter is set and the board_part is installed from the tcl app store.
Abnormal program termination (11)


Is any of you having the same issue?
I checked all the property to be set for the Vivado project in order to be exported for SDx, also within board_part property, and they are set correctly.

Thanks,
Giacomo

Re: SDSoC 2017.4 issues with board parts

Posted: Tue Aug 21, 2018 2:23 pm
by Timoteo
Attached the board files for EMC2-DP with TE0820 (REV02), TE0715-30 (REV 4) and FM191-RU.
Copy them into <vivadoinstallationpath>/Xilinx/Vivado/2017.4/data/boards/board_files/

EMC2-DP+TE0820+TE0715-30+FM191.zip
(9.55 MiB) Downloaded 3208 times


Attached the Repository where I have the SPI_US_Buffering IP and the SPI_rtl interface (to automate the DAC SPI interface with FM191)
IP_Repo.zip
(13.87 MiB) Downloaded 3227 times


Timoteo

Re: SDSoC 2017.4 issues with board parts

Posted: Thu Aug 23, 2018 6:35 pm
by Giacomo_Valente
Thanks, I tried them. Developing a classical project with Vivado 2017.4 and creating a platform for SDx works well.
Developing the HDMI test project from scratch in Vivado (the project that reads an image from DDR memory and puts in output) and exporting the platform for SDx, gives a timing violation, as reported in the attached timing_report. The curious fact is that the project builds correctly in Vivado, with the bitstream too.
Do you have any suggestion about this?