Tulipp Starter Kit - SATA Interface - Help

[Flemming_Christensen]

[Timoteo]

Dear all,
my company,ECHOES srl, bought the EMC2 equipped with TE0820 and we are having some troubles with the SATA controller on the PS of the ZynqUltrascale.
These are the steps that I followed to configure the SATA controller on the TE0820:
1. I activated the SATA controller from vivado on the GT Lane1, I checked the SATA ref clk value was 150 MHz (see SATA_config1.png and SATA_config2.png).
2. As Trenz suggests (https://wiki.trenz-electronic.de/displa ... Test+Board), I modified the fsbl of the zynq in order to have 150 MHz on the CLK2A/B of the Si5338 (U10 on the Trenz Schematic), attached you can find the file that I used to configure the clocks.
3. I enabled the SATA support in Linux as explained on (https://xilinx-wiki.atlassian.net/wiki/ ... 42339/SATA)
The petalinux is working but when I connect a SATA hard disk on the EMC2, I have this message:
[ 10.582912] ata2: SATA link down (SStatus 1 SControl 310)
[ 10.588233] ata2: EH complete
[ 10.591188] ata2: exception Emask 0x10 SAct 0x0 SErr 0x41c0000 action 0xe frozen
[ 10.598555] ata2: irq_stat 0x00000040, connection status changed
[ 10.604546] ata2: SError: { CommWake 10B8B Dispar DevExch }
[ 10.610105] ata2: limiting SATA link speed to 1.5 Gbps
[ 10.615222] ata2: hard resetting link
We tried different hard disks compatible with SATA 1,2 and 3, different cables etc... and we've got always the same error.
From https://ata.wiki.kernel.org/index.php/L ... r_messages I tried to understand the SError, it looks like that the problem is due to hardware.
By checking the TE0820 and EMC2 schematics, we noticed that the SATA lines on TE0820 and the SATA lines on EMC2 have a different polarity.
We asked to Sundance if this different polarity could be the problem, they affirm that this is actually a problem but at the moment they do not have the possibility to test the SATA controller on Zynq Ultrascale and emc2.
I tried to change the polarity of the clock generated from Si5338 by modifying registers 36-38 as explained in chap 9 of the "Si 533 8 R E F E R E N C E MANUAL" but this modification doesn't have success.
I would like to know if there is a way of changing the SATA line polarity from the C driver or directly from Vivado.
From the UG1085 it seems that one of the main functionality of the PS-GTR lines is "D+/D- lane reversal for flexible board integration" (pag 789), but honestly I do not get where to apply these changes for the SATA controller.
Could you help me to solve this problem?
Thank you very much for your attention
Best Regards
Dario

Dear Dario,
we have test SATA on our TE0808/TE0807/TE0803 series there was no additional changes on petalinux necessary. SATA kernel configuration and device tree was done correctly with petalinux HDF import.
I did not really know, why you change polarity of the reference CLK on the SI5338? Why should this help?
I did not check Sundance EMC2 schematics, but I think you mean P/N of the signal lanes are swapped. Correct?
Maybe this helps, if P/N is the problem:

https://forums.xilinx.com/t5/Serial-Tra ... d-p/887755

Best regards
John Hartfiel

Dear John,
We also have test your SATA configuration with TEBF0808 + TE0803 and everything is perfectly working.
Yes, I mean that the SATA lines are swapped, I'll check the post you suggest and I'll let you know.
About the clock polarity, I tried to see if the problem was how the bits are decoded but actually this could not be the problem because of the 8b/10b decoding. In fact, the clock is recovered throughout the data lines transitions. Basically it was an attempt based on a wrong assumption, but low time consuming .
Thank you for the prompt reply.
Regards
Dario

Dear John,
I finally succeed to make the SATA controller working.
The registers involved in the swap polarity are:
L1_TX_ANA_TM13 (absolute address 0xFD404034) (bit 3 and bit 2)
L1_TM_MISC1 (absolute address 0xFD405898) bit 7
I modified the fsbl, by inserting a function named XFsbl_emc2swapserdpol() in xfsbl_board.c and then I added this function to XFsbl_BoardInit().
Do you know a better place where I should insert these modifications? Any suggestion is welcomed.
The important thing to remember, at least in this case, is to write 0xC in the register L1_TX_ANA_TM13, the other values 0x4 (bit2) or 0x8(bit3) doesn't make petalinux happy, this was the error I had
ata2: softreset failed (1st FIS failed) [ 72.936506]
ata2: hard resetting link intercafe in a reset state.
But when I wrote 0xC the OS recognised my hard drive after a couple of attempt:
[ 3.820134] ata2: SATA link down (SStatus 1 SControl 330)
[ 3.825471] ata2: exception Emask 0x10 SAct 0x0 SErr 0x41c0000 action 0xe frozen t4
[ 3.833085] ata2: irq_stat 0x00000040, connection status changed
[ 3.839075] ata2: SError: { CommWake 10B8B Dispar DevExch }
[ 3.844634] ata2: hard resetting link
[ 6.070926] ata2: SATA link down (SStatus 1 SControl 330)
[ 6.076245] ata2: EH complete
[ 6.079199] ata2: exception Emask 0x10 SAct 0x0 SErr 0x41c0000 action 0xe frozen
[ 6.086568] ata2: irq_stat 0x00000040, connection status changed
[ 6.092558] ata2: SError: { CommWake 10B8B Dispar DevExch }
[ 6.098115] ata2: limiting SATA link speed to 1.5 Gbps
[ 6.103234] ata2: hard resetting link
[ 6.978925] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 310)
[ 7.025984] ata2.00: ATA-7: MAXTOR STM3320820AS, 3.AAE, max UDMA/133
[ 7.032258] ata2.00: 625142448 sectors, multi 0: LBA48 NCQ (depth 31/32)
[ 7.084293] ata2.00: configured for UDMA/133
[ 7.088481] ata2: EH complete
So John, thank you very much for your link.
Best Regards
Dario

Dear all,
the problem with the SATA was the P/N swapping, I interact with Trenz to have a pointer where to change the polarity.
Hereunder you can have an idea of the solution.
Thank you also for your support,
Best Regards
Dario